information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg784 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., cmos 3 v/5 v, wide bandwidth quad 2:1 mux in chip scale package functional block diagram adg784 s1a s1b d1 s2a s2b s3b s3a s4a s4b d2 d3 d4 in en 1-of-2 decoder features low insertion loss and on resistance: 4 typical on-resistance flatness <2 bandwidth >200 mhz single 3 v/5 v supply operation rail-to-rail operation very low distortion: <1% low quiescent supply current (100 na typical) fast switching times t on 10 ns t off 4 ns ttl/cmos compatible for functionally equivalent devices in 16-lead qsop/ soic packages, see adg774 applications 100vg-anylan token ring 4 mbps/16 mbps atm25/155 nic adapter and hubs audio and video switching relay replacement general description the adg784 is a monolithic cmos device comprising four 2:1 multiplexer/demultiplexers with high impedance outputs. the cmos process provides low power dissipation yet gives high switching speed and low on resistance. the on-resistance variation is typically less than 0.5 with an input signal ranging from 0 v to 5 v. the bandwidth of the adg784 is greater than 200 mhz and this, coupled with low distortion (typically 0.5%), makes the part suitable for switching fast ethernet signals. the on-resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switch- ing audio signals. fast switching speed, coupled with high signal bandwidth, also makes the parts suitable for video signal switch- ing. cmos construction ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments. the adg784 operates from a single 3.3 v/5 v supply and is ttl logic compatible. the control logic for each switch is shown in the truth table. these switches conduct equally well in both directions when on, and have an input signal range that extends to the sup- plies. in the off condition, signal levels up to the supplies are blocked. the adg784 switches exhibit break-before- make switching action. product highlights 1. also available as adg774 in 16-lead qsop and soic. 2. wide bandwidth data rates >200 mhz. 3. ultralow power dissipation. 4. extended signal range. the adg784 is fabricated on a cmos process giving an increased signal range that fully extends to the supply rails. 5. low leakage over temperature. 6. break-before-make switching. this prevents channel shorting when the switches are config- ured as a multiplexer. 7. crosstalk is typically C70 db @ 30 mhz. 8. off isolation is typically C60 db @ 10 mhz. 9. available in chip scale package (csp). rev. a 2013 781/461-3113
C2C adg784Cspecifications b version t min to parameter 25 ct max unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.2 typ v d = 0 v to v dd , i s = C10 ma 5 max on resistance match between channels ( r on ) 0.15 typ v d = 0 v to v dd , i s = C10 ma 0.5 max on resistance flatness (r flat(on) ) 0.5 typ v d = 0 v to v dd ; i s = C10 ma 1 max leakage currents source off leakage i s (off) 0.01 na typ v d = 4.5 v, v s = 1 v; v d = 1 v, v s = 4.5 v; 0.5 1 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v d = 4.5 v, v s = 1 v; v d = 1 v, v s = 4.5 v; 0.5 1 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v d = v s = 4.5 v; v d = v s = 1 v; test circuit 3 0.5 1 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.001 a typ v in = v inl or v inh 0.5 a max dynamic characteristics 2 t on 10 ns typ r l = 100 , c l = 35 pf, 20 ns max v s = 3 v; test circuit 4 t off 4 ns typ r l = 100 , c l = 35 pf, 8 ns max v s = 3 v; test circuit 4 break-before-make time delay, t d 5 ns typ r l = 100 , c l = 35 pf, 1 ns min v s1 = v s2 = 5 v; test circuit 5 off isolation C65 db typ r l = 100 , f = 10 mhz; test circuit 7 channel-to-channel crosstalk C75 db typ r l = 100 , f = 10 mhz; test circuit 8 bandwidth C3 db 240 mhz typ r l = 100 ; test circuit 6 distortion 0.5 % typ r l = 100 charge injection 10 pc typ c l = 1 nf; test circuit 9 c s (off) 10 pf typ f = 1 khz c d (off) 20 pf typ f = 1 khz c d , c s (on) 30 pf typ f = 1 mhz power requirements v dd = 5.5 v digital inputs = 0 v or v dd i dd 1 a max 0.001 a typ i in 1 a typ v in = 5 v i o 100 ma max v s /v d = 0 v notes 1 temperature ranges are as follows: b version, C40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 5 v 10%, gnd = 0 v. all specifications t min to t max unless otherwise noted.) single supply rev. a
C3C adg784 b version t min to parameter 25 ct max unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )4 typ v d = 0 v to v dd , i s = C10 ma 10 max on resistance match between channels ( r on ) 0.15 typ v d = 0 v to v dd , i s = C10 ma 0.5 max on resistance flatness (r flat(on) ) 2 typ v d = 0 v to v dd , i s = C10 ma 4 max leakage currents source off leakage i s (off) 0.01 na typ v d = 3 v, v s = 1 v; v d = 1 v, v s = 3 v; 0.5 1 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v d = 3 v, v s = 1 v; v d = 1 v, v s = 3 v; 0.5 1 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v d = v s = 3 v; v d = v s = 1 v; test circuit 3 0.5 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.001 a typ v in = v inl or v inh 0.5 a max dynamic characteristics 2 t on 12 ns typ r l = 100 , c l = 35 pf, 25 ns max v s = 1.5 v; test circuit 4 t off 5 ns typ r l = 100 , c l = 35 pf, 10 ns max v s = 1.5 v; test circuit 4 break-before-make time delay, t d 5 ns typ r l = 100 , c l = 35 pf, 1 ns min v s1 = v s2 = 3 v; test circuit 5 off isolation C65 db typ r l = 50 , f = 10 mhz; test circuit 7 channel-to-channel crosstalk C75 db typ r l = 50 , f = 10 mhz; test circuit 8 bandwidth C3 db 240 mhz typ r l = 50 ; test circuit 6 distortion 2 % typ r l = 50 charge injection 3 pc typ c l = 1 nf; test circuit 9 c s (off) 10 pf typ f = 1 khz c d (off) 20 pf typ f = 1 khz c d , c s (on) 30 pf typ f = 1 mhz power requirements v dd = 3.3 v digital inputs = 0 v or v dd i dd 1 a max 0.001 a typ i in 1 a typ v in = 3 v i o 100 ma max v s /v d = 0 v notes 1 temperature ranges are as follows: b version, C40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 3 v 10%, gnd = 0 v. all specifications t min to t max unless otherwise noted.) single supply table i. truth table en in d1 d2 d3 d4 function 1 x hi-z hi-z hi-z hi-z disable 0 0 s1a s2a s3a s4a in = 0 0 1 s1b s2b s3b s4b in = 1 rev. a
adg784 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg784 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v analog, digital inputs 2 . . . . . . . . . . C0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . 100 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 300 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c chip scale package ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 32 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. pin configuration terminology v dd most positive power supply potential. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. en logic control input. r on ohmic resistance between d and s. r on on resistance match between any two channels i.e., r on max C r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resis- tance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. see test circuit 4. t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 90% points of both switches, when switching from one address state to another. see test circuit 5. crosstalk a measure of unwanted signal that is cou pled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. bandwidth frequency response of the switch in the on state measured at 3 db down. distortion r flat(on) /r l rev. a notes 1. nc = no connect. 2. exposed pad tied to substrate, gnd. 14 13 12 1 3 4 s4b 15 s4a d4 s3a 11 s3b s1a d1 2 s1b s2a 5 s2b 7 nc 6 d2 8 gnd 9 nc 10 d3 19 nc 20 in 18 v dd 17 nc 16 en adg784 top view (not to scale)
t a = 25 c v s or v d drain or source voltage C v 1.3 2.5 3.7 4.9 5.0 4.5 0 r on C 2.0 1.5 1.0 0.5 3.0 2.5 3.5 4.0 v dd = 2.7v v dd = 3.0v v dd = 4.5v v dd = 5.0v tpc 1. on resistance as a function of v d (v s ) for various single supplies v dd = 5v 3.0 0 r on C 1.5 1.0 0.5 2.0 2.5 v s or v o drain or source voltage C v 1.3 2.5 3.7 4.9 +85 c +25 c C40 c tpc 2. on resistance as a function of v d (v s ) for different temperatures with 5 v single supplies +85 c +25 c C40 c 4.5 0 r on C 2.0 1.5 1.0 3.0 2.5 3.5 4.0 0.5 v dd = 3v v s or v d drain or source voltage C v 0.6 1.1 1.6 2.1 2.6 tpc 3. on resistance as a function of v d (v s ) for different temperatures with 3 v single supplies v dd = 5v frequency C hz 0 10m 10k on response C db C4 C2 100k 1m 100m C6 tpc 4. on response vs. frequency frequency C hz 0 C10 C100 100k 1g 1m 10m 100m C40 C70 C80 C90 C20 C30 C60 C50 attenuation C db v dd = 5v r l = 100 tpc 5. off isolation vs. frequency frequency C hz 0 C10 C100 100k 1g 1m 10m 100m C40 C70 C80 C90 C20 C30 C60 C50 attenuation C db v dd = 5v r l = 100 v p-p = 0.316v tpc 6. crosstalk vs. frequency typical performance characteristicsCadg784 C5C rev. a
adg784 C6C adg784 transformer tx1 tx2 rx1 rx2 10 base tx+ 10 base txC 100 base tx+ 100 base txC 10 base tx+ 10 base txC 100 base tx+ 100 base txC 10 base tx 100 base tx rj45 figure 1. full duplex transceiver figure 4. line clamp 120 100 figure 3. line termination tx1 rx1 figure 2. loop back source voltage C v 20 5 C10 15 10 0 C5 0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 charge injection C pc v dd = 5v t a = 25 c tpc 7. charge injection vs. source voltage rev. a
adg784 C7C test circuits i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance sd v s a a v d i s (off) i d (off) test circuit 2. off leakage sd v s a v d i d (on) test circuit 3. on leakage 0.1 f 5v v s in sd v dd gnd r l 100 c l 35pf v out en 3v 50% 50% 90% 90% v in v out t on t off test circuit 4. switching times 0.1 f 5v v s en s1a d1 v dd gnd r l 100 c l 35pf v out s1b decoder v s 50% 50% v in v out t d t d 50% 50% 3v 0v v s test circuit 5. break-before-make time delay 0.1 f v dd gnd en 50 v out v s in d1 v in s1a adg784 50 network analyzer test circuit 6. bandwidth 0.1 f v dd gnd en 50 v out v s in d1 v in s1a adg784 50 network analyzer 50 test circuit 7. off isolation rev. a
C8C adg784 0.1 f v dd gnd en in v in 50 v s d1 s2a adg784 d2 50 network analyzer v out s1a 50 test circuit 8. channel-to-channel crosstalk 5v en s1a v dd c l 1nf s1b v in v out 3v v out q inj = c l v out c l 1nf c l 1nf c l 1nf d1 v out d2 v out d3 v out d4 v out adg784 1-of-2 decoder in s2a s2b s3a s3b s4a s4b v s r s test circuit 9. charge injection rev. a
adg784 rev. a | page 9 outline dimensions figure 37. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADG784BCPZ ?40 c to +85c 20-lead lfcsp_wq cp-20-6 ADG784BCPZ-reel ?40 c to +85c 20-lead lfcsp_wq cp-20-6 ADG784BCPZ-reel7 ?40 c to +85c 20-lead lfcsp_wq cp-20-6 1 z = rohs compliant part. revision history 2/13rev. 0 to rev. a changes to pin configuration ......................................................... 4 updated outline dimensions .......................................................... 9 changes to ordering guide ............................................................. 9 4/01revision 0: initial version 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd-1. bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 2.30 2.10 sq 2.00 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 08-16-2010-b ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02374-0-2/13(a)
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